The present invention relates to a semiconductor device having a buried-type element isolation structure, and a method of manufacturing such a semiconductor device, and more specifically, to a semiconductor device in which elements are isolated by STI (shallow trench isolation) and a method of manufacturing such a device.
As is known, semiconductor devices having a buried-type element isolation structure entail the advantages of decreasing the size of element isolation regions, and achieving a well structure capable of suppressing the capacitance of the diffusion layer and being suitable for high-speed operation device.
For example, in order to maintain the capacitance of the diffusion layer at low, it suffices only if the concentration of impurities in the portion of the substrate, which corresponds to the bottom surface of the diffusion layer, or the concentration in the well is set to be sufficiently low. However, when the well concentration is lowered excessively, punching through between diffusion layers becomes uncontrollable. In order to avoid this, the concentration in the portion of the substrate, which corresponds to the bottom surface of the buried element isolation structure, or the well concentration is selectively increased, and thus the reduction of the capacitance of the diffusion layer and the control of the punch-through between diffusion layers are achieved at the same time in conventional techniques.
However, as the semiconductor devices are downsized, the trench for the element isolation becomes shallower (which is so-called STI). Therefore, even with the method described above, it is becoming difficult to achieve the reduction of the capacitance of the diffusion layer and the control of the punch-through for the element isolation, at the same time.
The conventional technique mentioned above will now be briefly reviewed with reference to FIGS. 1A to 1D, which are cross sections illustrating a manufacturing step for manufacturing the conventional buried-type element isolation structure and drawback of such a conventional technique.
First, as shown in FIG. 1A, conventionally, a silicon oxide film 2 is formed to have a thickness of about 10 nm, on a semiconductor (silicon (Si)) substrate 1 by a thermal oxidation method or the like. Then, a silicon nitride film 3 is deposited to have a thickness of about 200 nm, on the silicon oxide film 2 by a chemical vapor growth method or the like. Further, thus resultant structure is treated in the following manner. That is, the silicon nitride film 3, the silicon oxide film 2 and the silicon substrate 1 are subjected to anisotropic etching one after another by a photo-etching method. Thus, a buried type element isolation trench 4 having a predetermined shape is made. After that, heat oxidation is carried out, and consequently, a silicon oxide film 5 having a thickness of, for example, about 15 nm is formed on the inner wall of the buried element isolation trench 4.
Next, as shown in FIG. 1B, for example, boron ions are implanted to the above-described structure at an acceleration voltage of 20 keV and a concentration of 1xc3x971013 cmxe2x88x922 in the case where the substrate (or well) 1 in the region where the buried element isolation trench 4 is formed is p-type. Or, for example, phosphor ions are implanted to the above-described structure at an acceleration voltage of 30 keV and a concentration of 1xc3x971013 cmxe2x88x922 in the case where the substrate (or well) 1 in the region where the buried element isolation trench 4 is formed is n-type. Thus, in a region of the substrate (or well) 1, which corresponds to the bottom portion of the buried element isolation trench 4, a punch-through suppression region 6 having the same conductivity type as that of the substrate (or well) of the region and having an impurity concentration higher than that of other substrate (or well) 1 located close thereto, is formed.
Further, to the structure shown in FIG. 1B, an insulating film 7 such as silicon oxide film is buried, and then the insulating film 7 is flattened by a CMP (chemical mechanical polish) method, or a resist etch back method or the like. Subsequently, the insulating film 7, the silicon nitride film 3 and the silicon oxide film 2 are removed except for the matter inside the buried element isolation trench 4, thus completing a buried type element isolation structure 7xe2x80x2 as shown in FIG. 1C.
Next, as shown in FIG. 1C, for example, arsenic ions are implanted to the above-described structure at an acceleration voltage of 40 keV and a concentration of 3xc3x971015 cmxe2x88x922 in the case where the substrate (or well) 1 in the region where the element isolation structure 7xe2x80x2 is formed is p-type. Or, for example, BF2 ions are implanted to the above-described structure at an acceleration voltage of 30 keV and a concentration of 3xc3x971015 cmxe2x88x922 in the case where the substrate (or well) 1 in the region where the element isolation structure 7xe2x80x2 is formed is n-type. Thus, a high-concentration diffusion layer region 8 is formed in a vicinity of the surface portion of the substrate (or well) 1.
After that, as shown in FIG. 1D, an interlayer insulating film 10 is deposited on the high-concentration diffusion layer region 8 and the element isolation structure 7xe2x80x2, and a contact 11 designed to make an electrical contact with the high-concentration diffusion layer region 8 is formed in the interlayer insulating film 10. Further, a metal wiring 12 which is connected to the contact 11 is formed on the interlayer insulating film 10.
However, the element isolation structure 7xe2x80x2 thus formed entails the following drawbacks.
That is, it is originally preferable that the high-concentration diffusion layer region 8 shown in FIG. 1C should be in contact with a substrate (or well) 1 of a lowest possible concentration, in order to keep the capacitance of the bottom surface at low. However, in the manufacturing step described above, the high-concentration diffusion layer region 8 and the punch-through suppression region 6 are brought into contact with each other in a region 9 located close to the element isolation structure 7xe2x80x2. Therefore, in the close region 9, the reduction of the capacitance cannot be realized, which is not preferable to increase the high-speed operation of the semiconductor device.
Further, as counter-measurements, there is a method of implanting ion only to the substrate (or well) 1, which corresponds to the bottom portion of the element isolation structure 7xe2x80x2, in order to suppress the punch-through. However, even in the method, impurities diffuse in the substrate (or well) 1 in the lateral direction. For this reason, in devices of the future, which have shallower element isolation structure 7xe2x80x2, it becomes difficult to reduce the capacitance of the diffusion layer.
More specifically, as the semiconductor device is downsized, the possibility where the punch-through suppression region 6 and the high-concentration diffusion layer region 8 are in contact with each other becomes higher. This is because although the high-concentration diffusion layer region 8 becomes thinner, the size of the punch-through suppression region 6 is not always reduced, in order to maintain the concentration of the impurities in the punch-through suppression region 6, which accords with the downsizing. Therefore, the high-concentration diffusion layer region 8 and the high-concentration punch-through suppression region 6 can be easily brought in contact with each other, and it becomes further difficult to form a low-capacitance diffusion layer.
Further, as can be seen in FIG. 1D, as the downsizing proceeds, the distance between the contact 11 used to obtain electrical contact with the high-concentration diffusion layer region 8, and the element isolation structure 7xe2x80x2 becomes shorter. Therefore, when a mask alignment error occurs during the photo-etching process, the contact 11 is overlaid upon the element isolation structure 7xe2x80x2.
When the above-described problem occurs, the overlying section 7a of the element isolation structure 7xe2x80x2 is etched when the contact hole for the contact 11 is made, and thus a junction leak is created between the high-concentration diffusion layer region 8 and the well.
The object of the invention is to provide a semiconductor device capable of a high performance, in which the capacitance of the high-concentration diffusion layer region can be suppressed at low even for a shallow or fine element isolation structure, and the occurrence of a junction leak between the high-concentration diffusion layer region and the well is prevented, and a method of manufacturing such a semiconductor device.
In order to achieve the above-described object of the present invention, there is provided a semiconductor device having a buried-type element isolation structure, comprising: a substrate or well region, of a first conductivity type; a buried element isolation trench formed in the substrate or well region of the first conductivity type; a high-concentration impurity region of the first conductivity type, formed in a section of the substrate or well region of the first conductivity type, which is located near a bottom surface of the buried-type element isolation trench; an element isolation structure portion formed within the buried-type element isolation trench; a diffusion layer region of a second conductivity, formed in a surface portion of the substrate or well region of the first conductivity type, except for a region where the element isolation structure portion is formed; an interlayer film deposited on the substrate or well region of the first conductivity type; and a contact section pierced through the interlayer film, to be connected to the diffusion layer region; wherein the element isolation structure portion is formed by burying an insulating film having an etching selectivity ratio to the interlayer film, in at least a side wall portion of the buried element isolation trench, the high-concentration impurity region is formed selectively lower than the bottom surface of the buried element isolation trench, at a predetermined distance from an end portion of the bottom surface of the buried element isolation trench, and the contact section is formed to extend over the diffusion layer region and the element isolation structure portion.
According to the present invention, there is further provided a method of manufacturing a semiconductor device having a buried-type element isolation structure, including: a substrate or well region, of a first conductivity type; a buried element isolation trench formed in the substrate or well region of the first conductivity type; a high-concentration impurity region of the first conductivity type, formed in a section of the substrate or well region of the first conductivity type, which is located near a bottom surface of the buried-type element isolation trench; an element isolation structure portion formed within the buried-type element isolation trench; a diffusion layer region of a second conductivity, formed in a surface portion of the substrate or well region of the first conductivity type, except for a region where the element isolation structure portion is formed; an interlayer film deposited on the substrate or well region of the first conductivity type; and a contact section pierced through the interlayer film, to be connected to the diffusion layer region; wherein, after an insulating film having an etching selectivity ratio to the interlayer film is formed in at least a side wall portion of the buried element isolation trench, impurities are introduced, so as to form the high-concentration impurity region at an inner side from an end portion of the bottom surface of the buried element isolation trench by a distance determined by a thickness of the insulating layer, and the contact section is formed to extend over the diffusion layer region and the element isolation structure portion.
According to the present invention, there is still further provided a method of manufacturing a semiconductor device, comprising: the first step of forming an oxide film on a substrate or well region, of a first conductivity type; the second step of forming a mask film to make a buried element isolation trench, on the oxide film; the third step of making a buried element isolation trench by processing the mask film, the oxide film and the substrate or well region, with anisotropic etching; the fourth step of forming an insulating film along an inner surface of the buried element isolation trench; the fifth step of forming a high-concentration impurity region of the first conductivity type, formed selectively in a section of the substrate or well region of the first conductivity type, which is located near a bottom surface of the buried-type element isolation trench; the sixth step of forming an element isolation structure portion by burying a filler member in the buried-type element isolation trench; the seventh step of forming a diffusion layer region of a second conductivity, in a surface portion of the substrate or well region of the first conductivity type, except for a region where the element isolation structure portion is formed; the eighth step of depositing an interlayer film having an etching selectivity ratio to the insulating film, on an entire surface; and the ninth step of making a contact section pierced through the interlayer film, to be connected to the diffusion layer region in a self-alignment manner with respect to the element isolation structure portion.
With the semiconductor device and the manufacturing method of the present invention, it becomes possible to form an ion-implanted region used for the punch-through suppression, selectively in the bottom section of the STI in a self-alignment manner. More specifically, a side wall is formed on a side surface of a trench after the formation of the trench of the STI, and the ion implantation of impurities into the structure is performed, thus forming a punch-through suppression region. In this manner, the punch-through control region is formed selectively at the bottom portion of the STI, and therefore an increase in the capacitance of the diffusion layer, which is caused by the diffusion of impurities in the lateral direction, can be suppressed.
Further, when a filler member is buried into the structure, it is filled into a front taper shape. Therefore, even if the trench itself has a rectangular shape, it is possible to bury the filler member into the trench without creating a void.
Alternatively, according to the semiconductor device and the manufacturing method, of another aspect of the present invention, a filler member is buried into a trench at a degree about equivalent to the amount of the ion implantation to the bottom portion, and impurities are ion-implanted to the bottom portion of the STI. After that, the trench is completely filled with the filler member. With this structure, it becomes possible to provide an offset in a self-alignment manner with respect to the side wall of the STI. Further, the offset serves as a buffer while the impurities implanted to the bottom portion of the STI diffuse, and thus it is possible to prevent the diffusion of the impurities to the element region.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.